In recent years, there have been great advancements in the speed, power, and complexity of integrated circuits, such as application specific integrated circuit (ASIC) chips, random access memory (RAM) chips, microprocessor (uP) chips, and the like. These advancements have made possible the development of system-on-a-chip (SOC) devices. A SOC device integrates into a single chip all (or nearly all) of the components of a complex electronic system, such as a wireless receiver (i.e., cell phone, a television receiver, and the like). SOC devices greatly reduce the size, cost, and power consumption of the overall system.
Reductions in power consumption are particularly important in SOC devices. SOC devices are frequently used in portable devices that operate on battery power. Since maximizing battery life is a critical design objective in a portable device, it is essential to minimize the power consumption of SOC devices that may be used in the portable device. Furthermore, even if an SOC device is not used in a portable device, minimizing power consumption is still an important objective. The increased use of a wide variety of electronic products by consumers and businesses has caused corresponding increases in the electrical utility bills of homeowners and business operators. The increased use of electronic products also is a major contributor to the increased electrical demand that has caused highly publicized power shortages in the United States, particularly California.
To minimize power consumption in electronic devices, particularly SOC devices, many manufacturers have reduced the voltage levels at which electronic components operate. Low power integrated circuit (IC) technology operating at +3.3 volts replaced IC technology operating at +5.0 volts. The +3.3 volt IC technology was, in turn, replaced by +1.6 volt IC technology in many applications, particularly microprocessor and memory applications.
However, as the operating voltage of an integrated circuit is reduced, the noise margins of the integrated circuit are also reduced. Thus, an integrated circuit operating at +1.5 volts has smaller noise margins than a circuit operating at +3.3 volts. In deep submicron VLSI designs, two voltage sources for a chip design are common. One voltage source is an internal core power supply voltage (i.e., VDD) that has a lower swing voltage than the second voltage source, which provides the input/output (I/O) pad ring voltage (i.e., VDDIO). Common range values may include a VDD of 1-1.5 volts and a VDDIO range of 2.3-3.6 volts.
The internal core circuitry running on VDD typically uses thin gate oxides and cannot tolerate the higher external voltages of 2.3-3.6 volts. The transistors used in the pad rings, which interface off the chip to the board and surrounding chips, use a thicker gate oxide and larger minimum L than internal transistors and hence can handle the larger external voltages.
Many processing systems implement states in which the output power supply, VDDIO, is powered up while the internal core power supply, VDD, is zero, or, alternatively, states in which VDDIO is zero and VDD is powered up. FIG. 2 illustrates power monitor circuit 200 according to one embodiment, of the prior art. Power monitor circuit 200 comprises resistor 205, resistor 210, capacitor 215, and an inverter formed by PMOS transistor 220 and NMOS transistor 225.
Power monitor circuit 200 monitors a power supply, VDDIO. When VDDIO is fully powered up, it is greater in voltage than another supply, VDD, which becomes valid sometime before VDDIO is powered up. The purpose of power monitor circuit 200 is to issue a high signal (i.e., a Logic 1) when VDD is valid and VDDIO is not and to issue a low signal (i.e., a Logic 0) when VDDIO becomes valid.
The most common way to detect a valid VDDIO is to use a voltage divider, such as the midpoint between resistors 205 and resistor 210, which serves as the input to the inverter formed by transistors 220 and 225. The ratio of resistors 205 and 210, and the sizing of transistors 220 and 225 determine the trip point where VDDIO is considered a high (Logic 1). Capacitor 215 may be placed on the input of the inverter to prevent power monitor circuit 200 from responding to noise on VDDIO as it powers up.
When VDDIO is initially OFF and VDD is initially ON, the input to the inverter is Logic 0 (i.e., grounded by resistor 210.
Hence the output, OUT, of the inverter is Logic 1. When VDDIO is ON, the voltage at the junction of resistors 205 and 210 goes to Logic 1 (since resistor 210 is typically much larger than resistor 205). Thus, the output, OUT, of the inverter is Logic 0. The problem with power monitor circuit 200 is that it burns DC current when VDDIO is ON.
Therefore, there is a need in the art for integrated circuits in which output line drivers may be powered up to a known state while internal core circuitry is not powered up. More particularly, there is a need for improved integrated circuits in which the output of a power supply for the output line drivers may be monitored without consuming an unnecessary amount of power.